After discussing their plans to introduce an external version of PCIExpress which is set to rival Intel Thunderbolt high-speedinterconnect, the PCI SIG has begun working on new standards,the PCI Express 4.0, which will increase the bandwidth available toadd-on card use.
The announcement was made by chairman Al Yanes PCI-SIG (PCISpecial Interest Group) in a press conference at the group's annualdeveloper conference.
"Our initial report yesterday was the PCI Express 4.0 is a worthy -we have to work out the details, but feasible," says Mr Yanes.
In order to develop this new standard, the PCI SIG has formed anexploratory group includes members from companies such asAMD, Hewlett-Packard, IBM and Intel.
According to EETimes, this is a simulation using a variety of datachips, channel, and packet sockets and have determined that thethroughput of at least 16 GT / s PCIe Gen feasible to 4. The experts are expected to submit its final report until later this year.
Now, it seems that to achieve high transfer rates required by the fourth iteration of PCI Express, the scientists should focus more on the board level where the signal passes through the channel and less on developing a special chip.
As a result, PCI Express Gen 4 can be limited to a distance of about eight to 12 inches long, compared with 20-inch maximumthat can be borne by the PCIe Gen 3.
In addition to increasing the transfer speed of a standard,scientists will also look into reducing the latency of PCIe Gen 4 as well as other aspects of standards such as forward error correction, deeper pipelining and fault reporting and control.
PCI Express 3.0 specification was released in November last year and the PCI SIG targeting a four-year release cycle for PCIExpress, so the Gen 4 is expected in late 2014 or early 2015.
The announcement was made by chairman Al Yanes PCI-SIG (PCISpecial Interest Group) in a press conference at the group's annualdeveloper conference.
"Our initial report yesterday was the PCI Express 4.0 is a worthy -we have to work out the details, but feasible," says Mr Yanes.
In order to develop this new standard, the PCI SIG has formed anexploratory group includes members from companies such asAMD, Hewlett-Packard, IBM and Intel.
According to EETimes, this is a simulation using a variety of datachips, channel, and packet sockets and have determined that thethroughput of at least 16 GT / s PCIe Gen feasible to 4. The experts are expected to submit its final report until later this year.
Now, it seems that to achieve high transfer rates required by the fourth iteration of PCI Express, the scientists should focus more on the board level where the signal passes through the channel and less on developing a special chip.
As a result, PCI Express Gen 4 can be limited to a distance of about eight to 12 inches long, compared with 20-inch maximumthat can be borne by the PCIe Gen 3.
In addition to increasing the transfer speed of a standard,scientists will also look into reducing the latency of PCIe Gen 4 as well as other aspects of standards such as forward error correction, deeper pipelining and fault reporting and control.
PCI Express 3.0 specification was released in November last year and the PCI SIG targeting a four-year release cycle for PCIExpress, so the Gen 4 is expected in late 2014 or early 2015.